Virtex-5 FPGA A new generation of Xilinx^® FPGA products

The Virtex^TM-5 is the latest generation of platform FPGA from Xilinx^®, where the process technology used to fabricate the chip has been reduced from 90nm in the previous generation to just 65nm. It is the second generation of Xilinx FPGA to use the ASMBL™ (pronounced “assemble”) [Advanced Silicon Modular Block] column-based architecture that enables Xilinx to fabricate four FPGA platforms with varying feature mixes suitable to different application areas.

Virtex-5 LX: High performance general logic applications
Virtex-5 LXT: High performance logic with advanced serial connectivity
Virtex-5 SXT: Signal processing applications
Virtex-5 FXT: Embedded systems


Features
The Virtex-5 can be considered to offer a superset of the features found in the Virtex-4: all of the functionality of the Virtex-4 is available, though some features have been enhanced and some totally new features have been added.

Logic Fabric - There is up to 50% speed improvement (one or two speed grade improvement over Virtex-4) and an improved routing architecture with enhanced diagonal routing. There is also a device migration facility allowing developers to move their designs between LX devices and other Virtex-5 family devices. True 6-input look-up tables (LUTs) are now a feature of the logic fabric.

Hard IP blocks – These provide pre-fabricated functionality at lower power than could be attained with soft IP designs in the logic fabric. Current FPGA application developers will be familiar with hard IP in the form of RocketIO™ GTP transceivers and embedded PowerPC™ 440 processors. Virtex-5 ‘T’ devices feature RocketIO with new power-optimized transceivers operating up to 3.2Gbps, while consuming just 100mW. A totally new feature is hard IP PCI Express^® 1.1 subsystem blocks that can be connected into the RocketIO transceivers. These blocks support x1, x2, x4 and x8 PCI Express.

DSP functions - are supported by improved DSP48E slices featuring dedicated 25-bit x 18-bit two’s complement multiplier, optional pipeline stages for enhanced performance, optional 48-bit accumulator (with optional cascade to 96-bits) for MAC operations, integrated adder and optional bitwise logic modes to provide unrivalled DSP support that is fully cascadable in the DSP column without using external routing resources.

550MHz, 36 Kbit block RAM/FIFOs - Include true dual port RAM cells with independent port width selection from x1 to x72. Also included is programmable multi-rate FIFO support logic (Full, Empty, Almost Full & Almost Empty flag support), optional pipelining and integrated error correction circuitry (ECC).

550MHz Clock technology - There are up to 6 clock management tiles (CMTs) each now containing two digital clock managers (DCMs) and one PLL (phase locked loop)/PMCD (phase-matched clock divider) for input jitter filtering, zero delay buffering, frequency synthesis and phase matched clock division.

High Performance SelectIO Technology - Provides the interface between the package pins and the internal configurable logic, supporting 1.2V to 3.3V I/O signalling with true on-chip differential terminations. Digitally Controlled Impedance (DCI) active terminations provide temperature/voltage compensation and optional series or parallel terminations. Flexible I/O banking means different banks can use different signalling voltages. Memory interface support is included. Signalling performance is up to:

• 800 Mbits/s HSTL & SSTL (single ended)
• 1.2 Gbits/s LVDS (differential pairs)
  

ChipSynch - In conjunction with SelectIO technology, this simplifies source synchronous interfaces and supplies per-bit de-skew in all I/O blocks (variable delay on all inputs & outputs), built-in SERDES logic with corresponding clock divider support in all I/O, supporting networking/telecomms interfaces up to 1.25 Gbits/s.

Power
The Virtex-5 addresses power consumption concerns by offering a 35% to 40% reduction in dynamic power consumption over the previous generation of FPGAs while keeping static power consumption at the same level.

VMETRO Virtex-5 Products
VMETRO has been working closely with Xilinx to bring the Virtex-5 to board level products as early as possible; providing our customers with a time-to-market edge over their competition.

For more background reading on the Virtex-5 FPGA, download backgrounder (108KB PDF) and read the Using Virtex-5 FPGAs in COTS board-level products whitepaper.

Download an overview of VMETRO's Virtex-5 Platform FPGA boards