RapidIO A Packet‑Switched Interconnect

RapidIO Interconnect
RapidIO^® is a packet‑switched interconnect targeted toward distributed‑memory systems and subsystems.

RapidIO has distinct advantages over alternative architectures for distributed multiprocessor systems. Instead of a hierarchal, spanning tree topology, such as found with PCI-X and PCI-Express, RapidIO supports peer to peer communications with dual-star, mesh, daisy-chained or tree topologies.

Other architectures, such as PCI, are based on the assumption of a central host and a common memory map shared among all devices. But many embedded systems have multiple distributed processors that can benefit greatly from having direct access to multiple different endpoints (I/O, memory controllers, or other processing elements).

RapidIO enables highly efficient data transfers in part through its provisions that enable multiple devices to share memory globally. RapidIO and its hardware-based message passing architecture were specifically designed for these types of distributed systems, thus enabling higher performance and reduced complexity for embedded applications.

The necessity to bridge PCI and RapidIO
Because the commercial server markets drive the design and production of many high performance I/O peripherals (fibre channel, Gigabit Ethernet, Infiniband, etc.), providers of I/O silicon overwhelmingly choose PCI/PCI-X/PCI-Express as the digital interface for their chipsets. These various server markets also facilitate a large breadth of options for I/O connectivity (graphics, video, firewire, USB, etc.) and long distance interfaces to larger network infrastructures, e.g. ATM to WAN.

The embedded systems market has historically not had the volume demand necessary to drive these high performance I/O silicon vendors to offer devices for architectures other than what would be found in mass market servers. Despite RapidIO’s many technical advantages, it is unlikely that it will be able to change this tradition.

However, for embedded system designers, availing of the latest I/O peripherals and other related silicon produced for high end commercial servers has and will continue to be a definitive requirement. It provides the ability to leverage mass economies of scale, access to mature software and device drivers, and a means of utilizing cutting edge technology for various I/O functionalities.

ASIC-based Bus Translation Bridges
Balancing this need for an interconnect with a truly distributed architecture, that can be found in RapidIO, with the requirement to interface to server I/O peripherals, based on PCI, generally requires embedded system designers to implement ASIC-based translation bridges. In this case, it would involve an ASIC bridge that has a PCI endpoint and a Serial RapidIO endpoint, with the bridge translating the PCI protocol (PCI, PCI-X, or PCI Express) to RapidIO. While providing essential functionality, these bridges have several performance drawbacks.

Regardless of fine tuning adjustable parameters, bus translation bridges will inevitably force retires and disconnects. Combined with limited FIFO’s and inefficient pre-fetching, this will result in performance penalties in terms of latency and throughput that can negatively impact the greater system.