Virtex-4 FPGA A Xilinx^® FPGA product

The Xilinx^® Virtex^TM-4 family of FPGAs includes three domain-optimized platforms: the FX, the SX, and the LX.  The FX is the direct upgrade path from the well known Virtex-II Pro.  It is the only member of the Virtex-4 family to include embedded PowerPC processors and RocketIO^TM MGT SerDes, essential for implementing high speed serial links required by protocols such as Serial RapidIO^®, PCI Express^®, and Aurora^™.

The SX device is particularly unique in its number of DSP slices. It does not have embedded PowerPCs or RocketIO MGT SerDes, and is comparatively small in its available number of FPGA slices. 

Like the SX device, the LX device does not include embedded PowerPCs or RocketIO MGTs. The LX device is notable in the large amount of FPGA slices that it provides for logic intensive implementations.

Again, it should be noted that while the SX and LX series offer tremendous DSP and logic capabilities, they do not include RocketIO MGTs and thus can not directly interface with serial interconnects such as Serial RapidIO, PCI Express, Aurora, etc. Pairing these FPGAs with external SerDes would be especially challenging as the Xilinx Serial RapidIO, PCI-Express, and Aurora IP cores could not be readily utilized. Instead, practical implementations of the SX and LX devices require pairing them in combination with a Virtex-II Pro or Virtex-4 FX device (each of which do include MGTs) in order to utilize these powerful FPGAs with serial interconnects.

SX55 and Virtex-4 DSP Slices
The Virtex-4 SX55 is the largest device available in the SX family.

DSP slices are unique to the Virtex-4 FX, SX, and LX platforms. In the Virtex-II Pro and other FPGA families, only multipliers are offered thereby requiring all additions, subtractions, etc. to be implemented in logic.

The 512 DSP slices in the SX55 FPGA can perform 18 bit multiplications, accumulate 48 bit sums of these 36 bit products, or add these products to the output of the adjacent DSP slice. These functions are all part of the FPGA hardware, do not consume FPGA slices, and have register structures promoting efficient pipelined operations within and between the DSP slices. Practical clock rates of 250 to 350 MHz for these devices produce a theoretical 130 to 180 billion multiply/accumulate operations per second.

LX160 and Virtex-4 Logic Slices
It can sometimes be difficult to predict logic resource utilization requirements in advance of RTL implementation. The LX family addresses this concern by offering massive logic densities. In the Xilinx Virtex-4 portfolio, the LX160 is second in size only to the LX200. It offers over 67,000 FPGA slices for logic-centric applications requiring maximum gate count.

While using RTL abstraction tools such as The MathWork’s Simulink and Xilinx System Generator can reduce development time, resulting compiled VHDL can be verbose and require many more slices than might otherwise be required from hand coded state machines. The LX160 counters this concern by providing a large platform that provides the equivalent of approximately 15 million ASIC gates.