| Mezzanine Sites |
Two independent mezzanine sites each support PMCs or XMCs. The PMC sites are provided with 3.3V, 5V, and +/- 12V from the VME backplane. Each site can be configured for any one of the following modes of operation:
| PMC: |
PCI 2.3 in 32-bit or 64-bit mode @ 33MHz or 66MHz
PCI-X in 64-bit mode @ 66MHz or 133MHz |
| XMC: |
Serial RapidIO x4
Aurora (four MGTs) |
Mezzanine sites comply with IEEE P1386/P1386.1 CMC/PMC draft standard, ANSI/VITA 20-2001 (R2005), ANSI/VITA 32-2003, ANSI/VITA 35-2000, ANSI/VITA 39-2003, VITA 42.0-2005: drafts VITA 42.2 and VITA 42.5. |
| PMC J4-to-P2 |
The J4 connector on each mezzanine site interfaces to the VME P2 backplane connector in compliance with ANSI/VITA 35-2000 to support, for example, two RACE++ or two StarFabric ports on P2.
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| Serial RapidIO ports on P0 |
Two independent, full duplex Serial RapidIO x4 ports on the VXS P0 multi-gig connector in compliance with the VITA 41.2-200x draft standard.
|
| Aurora ports on P0 |
Two independent Aurora ports, each with four MGTs, can be configured to the VXS P0 connector in compliance with the VITA 41.5-200x and VITA 55 draft standards. These ports can be configured instead of the Serial RapidIO ports on P0, but not in addition to them. |
| CoSine Compute Nodes |
The MM-1550 is equipped with two independent CoSine Compute Nodes (CCN). Each CCN includes a Xilinx 2VP100 FPGA, Xilinx Virtex-4 LX160, two PowerPC processors, one Primary DDR array, two PowerPC local DDR arrays, four banks of QDR II SRAM, two PowerPC Flash arrays, and FPGA platform Flash arrays.
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| PowerPC Processors |
Each CCN contains two independent IBM 405GP PowerPC processors, providing four total processors on the MM-1550. |
| Primary DDR Arrays |
Each multi-ported Primary DDR array can be configured with 256MB, 512MB, or 1GB of DDR memory with ECC per CCN, for a total of up to 2GB on the MM-1550. |
| ECC |
An ECC engine on the Primary DDR array detects and corrects all single-bit errors, detects all double-bit errors, and some three and four bit errors within the same nibble. |
| Processor Local DDR |
Each PowerPC processor has 128MB of local DDR memory. |
| QDR II SRAM |
Each CCN contains 36MB of QDR II SRAM local to the Virtex-4 LX160 for buffering UPL processing operations. |
| FPGA Platform Flash |
Each CCN is equipped with FPGA platform Flash independent to each FPGA for multiple bitstreams and independent reconfiguration. |
| Processor Local Flash |
Each PowerPC has 32MB of processor programmable Flash and is capable of storing multiple boot images. |
| Protected Access |
For security against inadvertent Flash programming or corruption, a hardware switch is provided to disable the write enable line to the Flash devices along with additional high security capabilities. |
| Ethernet |
Each CCN has one 10/100 Ethernet interface shared between the two PowerPCs for SNMP command and control, debug, and downloading remote boot images or bitstreams. |
| On-board Serial RapidIO x4 Connectivity |
On-board crossbar switch provides simultaneous, non-blocking communication for six independent, full duplex Serial RapidIO x4 ports (two CCN ports, two P0 ports, two optional XMC ports).
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| VME320 Interface |
VME interface on P1 supports master/slave VME32, VME64, or VME 2eSST communications.
|
| Debug Ports |
Debug ports include four RS-232 UART consoles, one board/system push button reset switch, and two processor JTAG debug ports. Debug ports are available out the front panel or backplane via P0. |
| Status Indicators |
Four front panel LEDs indicate Ethernet and CCN status. Each CoSine LED is software programmable. |
| Power Rails |
+3.3V, +5V, +/-12V supply. Requires two amps per pin per VITA 1.7 draft standard. Contact factory for specific power requirements. |
| Physical Dimensions |
Height: 233.4 mm (9.2 in.)
Depth: 160 mm (6.3 in.)
Front Panel Height: 261.8 mm (10.3 in.) |
Width: 19.8 mm (0.8 in.)
Max. Component Height: 14.8 mm (0.58 in.) |