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Embedded Computing |
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Digital Signal Processors |
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FPGA Processors |
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- Virtex-5 FPGA - |
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VPX - 4x V5 |
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VPX 2xV5 & 2xPowerPC |
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VPX - 2x V5 & PowerPC |
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VXS - V5 & PowerPC |
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PCI - V5 Digital IO |
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PMC - V5 Digital IO |
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XMC - V5 Analog 1.5GS |
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XMC - V5 Analog 3GS |
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- Virtex-4 FPGA - |
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VPX - V4 for DSP |
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VPX - V4 for Logic |
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VXS - V4 for DSP |
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VXS - V4 for Logic |
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VXS - V4 IO Controller |
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PMC - V4 Logic Node |
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PMC - V4 DSP Node |
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PMC - V4 Dual Logic |
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- Virtex-II Pro - |
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PMC - V2Pro Digital IO |
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VXS - V2Pro & PowerPC |
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PMC - V2Pro Fiber IO |
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3U - V2Pro & PowerPC |
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- Tools - |
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FPGA Resources |
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FPGA Toolkit |
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Single Board Computers |
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Switch Cards |
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Digital I/O |
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Analog I/O |
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Fiber Optic I/O |
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Carriers |
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Buffer Memory Nodes |
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Ethernet |
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Chassis |
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Software |
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IP Cores |
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Mature Products |
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Data Recording & Storage |
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Protocol & Bus Analyzers |
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Network Storage |
The MM-6494D is a Type B Daughtercard with up to 4GB of SDRAM and two independent RACE++ ports for use in signal and image processing applications with intensive data streaming requirements. The card can be plugged into a single daughtercard site on a MCJ6, MCJ9, MCH6 or MCH9 to provide a large buffer for incoming and outgoing data.
A large front or rear end buffer is a fundamental element to optimizing system performance in stream computing applications. Individual compute nodes can then receive, process and transfer streaming data at will, which can greatly reduce total compute time and arbitration and overhead for the host, maximizing overall system performance.
The MM-6494D has two RACE++ ports. Each of these two ports has an individual memory bank with up to 4GB of SDRAM. Each memory bank can be accessed simultaneously, but only through its dedicated RACE++ port. Each port supports burst transfer rates of up to 267 MB/s.
This architecture provides that data from the two independent RACE++ ports can be directly transmitted or received from any one of two "non-busy" memory banks to achieve an aggregate transfer rate of up to 533 MB/s.
Reliability is ensured by burn-in and running memory diagnostics that check operations while temperature-cycling the boards.
Last updated: Jul 17 2008, 03:35PM