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Embedded Computing |
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Digital Signal Processors |
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FPGA Processors |
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- Virtex-5 FPGA - |
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VPX - 4x V5 |
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VPX 2xV5 & 2xPowerPC |
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VPX - 2x V5 & PowerPC |
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VXS - V5 & PowerPC |
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PCI - V5 Digital IO |
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PMC - V5 Digital IO |
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XMC - V5 Analog 1.5GS |
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XMC - V5 Analog 3GS |
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- Virtex-4 FPGA - |
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VPX - V4 for DSP |
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VPX - V4 for Logic |
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VXS - V4 for DSP |
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VXS - V4 for Logic |
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VXS - V4 IO Controller |
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PMC - V4 Logic Node |
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PMC - V4 DSP Node |
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PMC - V4 Dual Logic |
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- Virtex-II Pro - |
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PMC - V2Pro Digital IO |
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VXS - V2Pro & PowerPC |
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PMC - V2Pro Fiber IO |
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3U - V2Pro & PowerPC |
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- Tools - |
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FPGA Resources |
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FPGA Toolkit |
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Single Board Computers |
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Switch Cards |
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Digital I/O |
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Analog I/O |
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Fiber Optic I/O |
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Carriers |
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Buffer Memory Nodes |
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Ethernet |
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Chassis |
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Software |
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IP Cores |
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Mature Products |
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Data Recording & Storage |
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Protocol & Bus Analyzers |
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Network Storage |
The MM-6296 provides up to 1gigabyte of DRAM memory with a 64-bit transfer at up to 80 megabytes/sec. It is available in a standard operating temperature version (the MM-6296D) or an extended temperature version (the MM-6296DR).
The MM-6296 supports block modes of A32/A24,D64/D32/D16/D8. Bank switching is provided through a Control Software Register in the I/O which expands to more than 4 gigabytes.
Each 8-bit byte has an associated bit for parity error detection. Parity status is stored and transmitted via BERR*; asserting BERR* inhibits the DTAK* signal during memory read operations.
The MM-6296 is supported with anodized stiffeners to meet strenuous vibration requirements. All units are screened through a temperature cycling process from -15°C to +70°C for extended temperature applications. Each unit then goes through a rigorous quality inspection which includes a 48 hour burn-in process while running diagnostics.
Last updated: Oct 04 2007, 01:11AM