SBC731 6U VPX-REDI Single Board Computer with Serial RapidIO and PCI Express

The SBC731 is a VPX-REDI PowerPC™ single board computer with dual mezzanine sites and on-board Serial RapidIO^® (sRIO) and PCI Express^® (PCIe) fabric connectivity. Utilizing a Freescale Power Architecture™ MPC8641D processor, the dual-core design provides significant processing power while still meeting rugged, extended temperature convection and conduction-cooled requirements. Combining this processing power with the flexibility of dual PMC/XMC sites and sRIO and PCIe fabrics satisfies a variety of embedded applications.

Processing
At the heart of the SBC731 is a dual-core MPC8641D processor. Using the e600 core and the AltiVec^™ vector engine, each core is capable of running at speeds of 1.0, 1.33 or 1.5GHz. Customers can balance processing power with heat dissipation to best meet their requirements, choosing not only the frequency, but also a single or dual-core processor. Each core is supported with 1MB of L2 cache.

The MPC8641D’s memory controllers are 72-bits wide and run up to 600MHz, 64-bits for data and 8-bits for ECC. Each memory controller supports up to 1GB of DDR2 memory, providing up to 2GB of memory per board.

Connectivity
The MPC8641D on the SBC731 supports PCIe x8 through one fabric port. The eight PCIe lanes run at 2.5GHz and connect to a multi-port crossbar switch. The crossbar switch connects both XMC mezzanine sites, both PCIe-to-PCI-X bridges, and to a x8 or dual x4 connections to the backplane. This on-board connectivity allows XMC and PMC transfers to occur without passing through a processor, and also provides for an alternative path for processor communication and expansion to other mezzanine carriers.

The second fabric port supported by the MPC8641D is a sRIO x4 connection. Running at 3.125GHz, this connection routes to a crossbar switch. sRIO provides the primary backplane connectivity for systems based on the SBC731, and connects to the P1 fabric connector per VITA 46.3 standards. Incorporating a sRIO crossbar on every VPX board provides for a distributed switching architecture that allows for a passive backplane. With four x4 connections to the backplane, architectures range from a 5-slot full-mesh topology to a 16-slot VPX system in a standard chassis. There is also a build option that supports sRIO to the XMC mezzanine sites instead of PCIe. Finally, these additional sRIO connections can alternatively be routed to the backplane P6 connector, providing up to six sRIO ports when used in conjunction with the P1 fabric connector.

The latest incarnation of VME is also supported on the board. Running the 2eSST protocol, the VME interface provides backwards compatibility with VME64/32 systems, but with up to four times the bandwidth. This is done through the P2 backplane connector. The processor supports two Gigabit Ethernet connections, with one running to the front panel and the other to the backplane on the P4 connector. These connections can be used for command and control or as a data port depending on the application.

A break-out cable connecting to the front panel connector provides access to RS-232 connections for each processor core, Gigabit Ethernet, JTAG and a reset button.

Mezzanines
The SBC731 has the most flexible mezzanine architecture available for an embedded platform. Because today’s boards are so dense with components, most boards put restrictions on the mezzanine site capability, or reduce it down to a single site. However, with two full XMC/PMC sites that take advantage of the Jn4/Jn6 connectors, the SBC731 provides maximum I/O density and flexibility in the 6U form factor.

Based on the VITA 42 XMC standard, the Jn5 connectors can support PCIe x4/x8 or sRIO x4 depending on the build option. Those signals are routed through their respective crossbar. The Jn6 connectors can route up to 20 differential pairs to the backplane per VITA 46.9. This allows sensor data to be brought in directly from the backplane, or for XMC I/O to bypass the on-board processing and be used in another part of the system.

The mezzanine sites are also capable of supporting PMCs through the Jn1-3 connectors. Supporting 64-bit and 32-bit data paths, the signals can handle frequencies of 33/66/133MHz. The PCI/PCI-X signals connect to a bridge chip, which then connects to the PCIe crossbar. Finally, the Jn4 connector routes 64 signals from the connector, including 54 single-ended lines and up to 5 differential pairs going to either the System Control Node (SCN) FPGA or the P3/P5 backplane connectors. This data can be re-directed to the other mezzanine, interface with a processor, or be routed to the backplane through the SCN.

System Control and Chassis Management
The on-board SCN controls chassis management, power and temperature monitoring, bit stream encryption, and routing of single-ended I/Os. Users can take advantage of VMETRO’s default HDL functionality, or program their own logic into the SCN.

Software
The SBC731 has Board Support Package (BSP) support for VxWorks 6.x and Linux 2.6.x with associated APIs for ease of customer development. VMETRO’s FusionIPC, Inter-Processor Communication software stack for Distributed Multi-Processing (DMP) systems, is supported on the SBC731.

Ruggedization
Designed from the ground up for rugged deployment, the SBC7310 can be used in commercial, extended-temperature convection-cooled, conduction-cooled, and liquid-cooled (LFT) environments.