Questions
What FPGAs are available on the PMC-FPGA03F?
What development tools will I need to procure?
What Pn4 / Jn4 (P14) User I/O connector routing is available on the PMC-FPGA03/F?
What clocks are available for me to use in the FPGA?
What is the clock rate that the DDR SDRAMs operate at, and what is their effective throughput?
What is the clock rate of the QDR devices and what is their effective throughput?
What is the maximum RocketIO signaling speed via the P14 User I/O connector?
What is the significance of the reference clocks REFCLK/BREFCLK?
What is the PMC-FPGA03F Fiber Optic Transceiver Specification?
What bandwidth is available through the PCI interface?
How much external memory is available?
Are there any software examples with the board?
Can I buy a rugged version of this board?
Q: What FPGAs are available on the PMC-FPGA03F?
A: The default FPGA fitted is the XC2VP50-6. ‘-6’ is the speed grade of the device.
Q: What development tools will I need to procure?
A: Essential tools are Xilinx ISE Foundation 6.2.03ii or later, using XST for synthesis.
Optional tools include:
Other synthesis tools can be used but are not directly supported; Synplify 7.x can generally be used with little trouble (a porting guide for it is included).
ModelSim XE simulator (for small projects) or ModelSim PE/SE (for large projects). Other simulation tools may be usable but typically require some porting effort.
Hardware Debugging: Xilinx ChipScope FPGA logic analyzer. Users must also purchase a JTAG pod such as Xilinx’s Parallel Cable IV to use these tools.
Q: What Pn4 / Jn4 (P14) User I/O connector routing is available on the PMC-FPGA03/F?
A: The 64 PMC User I/O connector pins (P14) are routed directly to the FPGA.
Parallel I/O: differential routing, with optional 100R termination, is used. Signals are paired on adjacent P14 pins, with the –ve side on the lower numbered pin: for example, pin 1 -ve, pin 3 +ve; pin 2 –ve, pin 4 +ve. The signals can use either single-ended or differential I/O standards, as supported by the Virtex-II SelectIO cells. VCCO can be set to 3.3V, 2.5V, 1.8V or 1.5V.
Q: What clocks are available for me to use in the FPGA?
A: There is a single external 80MHz clock input into the FPGA, the clock provides on the board that is available for use in the FPGA.
In addition there are DCM (Digital Clock Manager) components available in the Xilinx FPGA that can be used to generate and synthesize clocks, using the 80MHz local bus clock reference.
Q: I would like to use an external clock reference, Are there clock pins available on the board for me use?
A: Yes, there are four available on the front panel and four available on the Jn4 rear IO connector.
Q: What is the clock rate that the DDR SDRAMs operate at, and what is their effective throughput?
A: Two DDR SDRAM memory chips are fitted to the PMC-FPGA03.These are connected directly to the Xilinx FPGA as two independent 16 bit wide banks and are clocked at 125MHz. The peak bandwidth is 500Mbytes/sec in one direction. As with all page-based SDRAM devices, the throughput depends on how randomly the memory is accessed. These are the SDRAM timing parameters:
- Cas latency of 2 clks.
- tRAS of 5 clks (minimum delay from row activate to row precharge).
- tRP of 2 clks (minimum delay from row precharge to row activate).
- tRCD of 2 clks (minimum delay from row activate to read/write).
- tRC of 7 clks (Row cycle time - minimum delay between row activate and same row activate, and between refresh and row activate commands).
Q: What is the clock rate of the QDR devices and what is their effective throughput?
A: The PMC-FPGA03 includes three 18-bit wide second generation Quad Data Rate (QDR-II) SRAMs, all clocked at 125MHz. QDR memories have separate read and write data buses, which are both double data rate (clocking data on the rising and falling edge of the clock). When clocked at 125MHz, each device sustains a simultaneous read and write bandwidth of 500MBytes/second. VMETRO provides a library component to control these memories so that each is accessed as an independent standard synchronous SRAM, connected through separate 36-bit SDR read and write data buses, and read and write address buses.
Q: What is the maximum RocketIO signalling speed via the P14 User I/O connector?
A: The limiting factors to the signalling bandwidth through the PMC user I/O connector are the quality of the connectors in the communications path and the routing on the particular motherboard. The P14 signals have been loop-back tested to 2.0 GHz, however, these loop-back signal lines are very short and of matched length.
In a real system, it is likely that the routing from P14 to the VME P2/P0 connector will not be of matched-length and nor will the routing on the board communicating with the PMC-FPGA03/F. In between these communicating boards will be a number of connectors and a backplane which are not designed for multi-gigabit communications. All of these factors will add up to reduce the maximum signalling speed below 1GHz, though the exact figure will be heavily system dependent.
Q: What is the significance of the reference clocks REFCLK/BREFCLK?
A: REFCLK and BREFCLK are generated from a source external to the FPGA on the PMC-FPGA03 which is connected to the FPGA as differential inputs. They form the reference from which the PLL architecture for the RocketIO multi-Gigabit transceivers (MGTs) are clocked. The RocketIO signaling speed is either 10x or 20x this reference frequency.
This source needs to be very low jitter and for serial speeds of 2.5GHz or higher, the BREFCLK source must be used as this input has been internally routed in the FPGA only to the closest transceivers (rather than the whole FPGA fabric, like REFCLK) to reduce jitter. There are two independent BREFCLK reference inputs, so when they are used on the PMC-FPGA03/F, the P14 user I/O transceivers may run at a different speed to those routed to the front panel.
Q: How many channels of Serial FPDP (or other RocketIO supported protocol) can be supported on the PCI bus?
A: There are two DMA channels available in the QL5064 each with a read and a write FIFO. When one channel of Multi-Gigabit data is input to the PMC-FPGA03/F and needs to be transferred to the PCI bus, the process is relatively simple. However, if the user has 2 or more input channels from the MGTs, then dataflow control becomes more complicated as:
- The full-speed raw bandwidth of two MGT channels is higher than the PCI bus will support.
- The individual channels need to be interleaved and DMAed across the PCI bus then reconstructed correctly at the data destination (e.g. host memory).
These problems can be mitigated if the user performs signal processing algorithms in the FPGA that reduce the data presented to the PCI bus to a manageable amount and transfers blocks of each channel’s data.
Q: What is the PMC-FPGA03F Fiber Optic Transceiver Specification?
Stratos Lightwave “Low Rider” RJ-Format Low Profile Optical Transceiver modules are used. Information can be obtained from www.stratoslightwave.com.
The standard build uses 2.125Gbit/sec "1x / 2x Fiber Channel Low Rider" multimode 850nm transceivers, part number LTL-ST11H. This is designed for 1x/2x Fiber Channel Applications, 850nm VCSEL, Multimode, for fibers up to 500m long.
Other fiber standards can be accommodated. Please contact your nearest sales representative to discuss your requirement.
Q: What is the maximum optical communication bandwidth on the PMC-FPGA03F?
Q: To what distance will the PMC-FPGA03F optical fiber communications operate?
The default built option uses a 106.25MHz BREFCLK and 850nm multimode transceivers, though there are a number of other hardware options supporting different signalling speeds and ranges:
| BREFCLK(MHz) | Data Rate (GHz) | Mode | Wavelength (nm) | Range (m) | Suitable for |
| 53.125 | 1.0625 | Single | 1310 | 10 000 | 1x Fiber Channel |
| 53.125 | 1.0625 | Multi | 850 | 550 | 1x Fiber Channel |
| 62.5 | 1.25 | Single | 1310 | 10 000 | Gigabit Ethernet |
| 62.5 | 1.25 | Multi | 850 | 500 | Gigabit Ethernet |
| 106.25 | 1.0625/2.125 | Multi | 850 | 500/300 | 1x/2x Fiber Channel |
| 125.0 | 2.5 | Multi | 850 | 150 | Infiniband, Serial FPDP |
| 159.375 | 3.125 | Multi | 850 | 100 | Pixelbus, RocketIO max |
Signaling distances are dependent on the type of fiber being used. The multimode figures here are the maximums using 50/125 fiber.
Note: The 'suitable for' column gives an example of the protocols that these signal speeds are associated with. There is currently NO FIRMWARE SUPPORT for any of these protocols. Please contact your nearest sales representative to discuss your requirement.
Q: What bandwidth is available through the PCI interface?
This bandwidth is heavily dependent on the chipset used by the host, but it is quite common to observe over 400Mbytes/s sustained data rates during DMA transfers.
Q: How much external memory is available?
2 banks DDR SDRAM (64Mbytes per bank)
3 banks QDR-II SRAM (up to 8Mx18-bit per bank)
The independent bank arrangement of both the SRAM and SDRAM provides users with the flexibility to utilize the memory in a way most consistent with the application requirements. For example, if the SDRAM is being used as a buffer pool for high bandwidth data, the memory may be used ‘ping-pong’ fashion: the FPGA emptying one buffer to process the data while the other buffer is filled by incoming data.
Q: Are there any software examples with the board?
Yes. VMETRO are constantly adding to the examples supplied with the software tools. Included are examples (which contain all host C/C++ source code and VHDL for the FPGA) to
- DMA to and from DDR SDRAM
- DMA to and from QDR SRAM
- DMA between fiber-optic channels and host platform
Q: Can I buy a rugged version of this board?
Conduction cooled boards are in the development roadmap. Contact VMETRO for further information.
RSS