Phoenix 6821 215 MSPS, 12-bit A/D with Virtex-II Pro FPGAs

The Phoenix 6821 is a complete high frequency, wide bandwidth channel ADC converter coupled to a powerful signal processing resource. The signal processing resource is provided by two Xilinx^® Virtex™ II Pro FPGAs, each of which contains two embedded PowerPC processors. A small portion of each FPGA is used to format the acquired data and to send it over VXS or FPDP connections. The bulk of the FPGAs is available for customer applications. The Phoenix 6821 is a 6U VMEBus card and is available in commercial and ruggedized options to suit the customer environment.

The TransComm™ communications suite is supported by the Phoenix 6821 to facilitate and simplify the rapid development of systems involving high speed communication between different elements.

Input Stage and A/D Converter
A front panel female SMA connector accepts an analog RF input at a full scale level of +8 dBm or +2 dBm (software selectable) into the primary of a RF transformer which presents a 50 ohm input impedance. The transformer offers a low-distortion path to the differential inputs of the Analog Devices AD9430 A/D, with a flat frequency response from 400 kHz to 700 MHz (standard).

Clocking, Gating and Triggering
The A/D converter sample clock can be sourced from an internal 210 MHz crystal oscillator or from an externally supplied sinusoidal clock at a maximum frequency of 215 MHz. This clock is accepted through a front panel SMA connector terminated in 50 ohms. An external LVDS bus supports synchronous data acquisition across multiple boards. This is ideal for applications such as multichannel radar systems.

Virtex-II Pro FPGAs
The Phoenix 6821 utilizes two Xilinx Virtex-II Pro Series FPGAs. Each FPGA is optionally equipped with 128 M of SDRAM and 16 MB of FLASH memory. Each Xilinx Virtex-II Pro FPGA accepts 12-bit signals at the sampling frequency from the A/D converter, and formats the data for transmission over VXS or FPDP. The FPGAs also act as controllers for other functions on the board including gating and triggering. Optional LVDS I/O is available through either the VMEbus P2 connector or a second-slot front panel mezzanine.

VXS Interface
The Phoenix 6821 provides a 4x full duplex VITA-41 VXS link to the VME P0 connector from each FPGA. Each 4x link supports data transfer rates of up to 1.25 GB/sec. These links support high speed serial protocols such as Aurora and TransComm.

FIFOs and FPDP Outputs
Following each FPGA are two 32-bit wide FIFO buffers with a standard depth of 32k words. These FIFOs are useful as elastic memory to support hard disk latencies in recording applications. A total of four FPDP output ports are available, two per FPGA, to support data transfers of 320 MB/sec each or greater. One port per FPGA is attached to the 6821 front panel, with the second attached to an optional second-slot front panel. A data demultiplexing mode splits the data stream between each pair of FPDP ports, reducing the output data rate by a factor of up to four (depending on the data packing mode and number of FPDP ports) to support slower FPDP devices.