AD3000 Single Channel 3 GSPS Analog to Digital Converter XMC/PMC module with User Programmable Virtex-5 SX95T/LX110T FPGA

The AD3000 closely couples a high performance Xilinx Virtex-5 FPGA to a high-speed analog input front end providing both processing and up to 3 GSPS acquisition in a single XMC/PMC card. The combination of a user programmable FPGA, data I/O sub-systems and multiple banks of fast memory provides a powerful platform for acquiring and processing high-speed data in one board. In addition to processing digitized data, the Xilinx Virtex-5 SXT or LXT FPGA is used to control the analog to digital converter and provides the off-board interfaces to either PCI-X or the multi-Gbps serial I/O used for the XMC interface.

The AD3000 is ideal for DSP applications including: Electronic Counter Measures (ECM), Spectral Analysis and Radar.

Analog I/O and FPGA Processing in One
The AD3000 is a combined acquisition and FPGA based data processing module. The majority of the Virtex-5 FPGA resources are available for user programmable processing and are supported by SRAM and SDRAM memories. Some applications that are be ideally suited for FPGA based processing include Digital Down Conversion (DDC), Fast Fourier Transforms (FFTs) and digital filters.

3 GSPS Analog Input
Analog to digital conversion is performed by a National Semiconductor ADC083000 device, which is an 8-bit, 3 GSPS ADC. The analog input stage is transformer AC coupled to the ADC via a balun. The full power input bandwidth of the AD3000 is 2.25 GHz (3dB), though input frequencies up to 3 GHz can also be sampled. Using the ADC’s built-in demultiplexer, digitized data is transferred to the FPGA using a 32-bit interface (4 samples in parallel) at one 8th of the sampling rate along with a quarter of clock frequency (double edge clocking) to match valid data.

Clocks, Triggers and Multi-board Synchronization
The AD3000 provides a front-panel MMCX connector for connecting an external sample clock source (required). The input clock rate to the AD3000 is ½ of the ADC sample rate as the ADC device uses double edge clocking (i.e. a 1.2 GHz clock source is required to digitize data at 2.4 GSPS).

A front panel mounted trigger input (TI) and a trigger output (TO) signal are connected to the FPGA via LVPECL I/O stages. This allows the FPGA to define the trigger mechanism through the application for maximum flexibility.

The AD3000 supports multi-board synchronization allowing all ADCs to be synchronized to a common clock source. When synchronized, all data will be aligned and coherent across multiple AD3000 boards. VMETRO’s XCLK1 clock generator is capable of providing this synchronized sample clock output to two or more AD3000 ADCs, providing support for features such as synchronous reset of the sample clock.

Xilinx Virtex-5 FPGA
The AD3000 can be fitted with either a Xilinx Virtex-5 SX95T or LX110T FPGA (contact factory for availability of LX155T or FX100T variants) allowing the AD3000 to be optimized to provide the largest amount of DSP capabilities or maximum amount of logic gates.

The FPGA is configured at power up from FLASH with a default image, a recovery image or an image the customer generates. In addition to FLASH configuration, new images can be downloaded from the host via the PCI or PCI Express interface. Software is provided to load new images into either FLASH or SRAM. Bit streams stored in SRAM benefit from faster downloads while bypassing non-volatile storage - useful for secure applications.

Multiple SDRAM and SRAM Banks
The AD3000 features both external SRAM and SDRAM connected to the FPGA. These can be used for buffering ADC data or for general purpose processing support.

The two 128 Mbyte DDR2 SDRAM banks on the AD3000 can be used in parallel to buffer digitized data. Each bank is 16-bits wide and clocked at up to 250 MHz for a net throughput of up to 1Gbyte/sec per bank. When sampling at 2 GSPS, the 256 Mbyte of SDRAM available on the AD3000 provides enough capacity to buffer more than 128 msec of continuous ADC data.

QDR2 SRAM provides higher bandwidth external memory. Two 2M x 36-bit banks are fitted on the AD3000 and clocked at up to 250 MHz for a net throughput of up to 2 Gbytes/sec per bank. Interleaved, the QDR2 SRAM banks have sufficient bandwidth to store and retrieve data at the maximum 3 GSPS data rate.

PCI/PCI-X, PCI Express and Multi-Gbps I/O
The AD3000 includes a PCI/PCI-X interface, supporting up to 133 MHz operation, and a PCI Express interface. These interfaces provide multi-channel DMA support.

The PCI Express interface uses the Virtex-5 FPGA’s RocketIO GTP transceivers and an embedded end-point controller. The Virtex-5 FPGA provides sixteen, full duplex high-speed serial communication links through RocketIO GTP transceivers. These links are evenly split between two XMC (VITA 42) connectors. Each link is able to operate at up to 3.2 Gbps (using an SX95T FPGA) and can be driven as independent data streams or bonded to create ‘fat pipes’ for fewer, but higher bandwidth, data streams. A built-in PCI Express end-point block allows x4 or x8 lane communications at 2.5Gbps. This is a hard IP block within the Virtex-5 FPGA, which can be bypassed for other protocols such as sFPDP.

Rugged Build Options
A range of environmental requirements are addressed by the AD3000: air-cooled benign, air-cooled extended temperature, air-cooled rugged and conduction-cooled. For conduction-cooled applications, the host board must be able to incorporate front panel I/O connections. Depending on the application, a suitable heatsink may be required for conduction-cooled builds.

FusionXF Software/HDL Support
VMETRO’s FusionXF software, HDL and utility suite provides examples and infrastructure for using the AD3000 or the AD3000 on one of VMETRO’s other Xilinx Virtex-5 and Virtex-4 FPGA-based products. This includes a C-API and sophisticated DMA support.