Related Products:
MM-1650 - VPX Serial RapidIO Intelligent IO Carrier with Dual User Programmable Virtex-4 LX160 FPGAs
MM-1600 - VPX Serial RapidIO Intelligent IO Carrier with dual User Programmable Virtex-4 SX55 FPGAs
MM-1550 - VXS Serial RapidIO Intelligent IO Carrier with dual User Programmable Virtex-4 LX160FPGAs
MM-1500 - VXS Serial RapidIO Intelligent IO Carrier with dual User Programmable Virtex-4 SX55 FPGAs

CoSine Applications


Synthetic Aperture Radar, Phased Array Radar, Software Defined Radio, Sonar, and signal intelligence such as SIGINT, COMINT, and ELINT are each primary applications that were specifically targeted from the outset of CoSine’s initial architectural design phase.

Other related applications involve masking and lithography for semiconductor equipment, data and file system compression for networked storage, image rendering for medical tomography, explosive detection systems, seismic processing and energy exploration.

FPGA based digital signal processing is particularly relevant to all of these applications because it provides the ability to perform multiple functions in parallel that would otherwise be executed in a serial mode on a conventional DSP or embedded processor. Algorithms for applications such as signal detection, smart antennas or RF baseband processing are often well suited to take advantage of internal FPGA resources such as multiply/accumulators, RAM, FIFO’s and look up tables (LUT’s).

For quicker development time at the cost of an optimally efficient logic implementation, CoSine also supports the use of MATLAB in combination with Simulink and Xilinx System Generator. As a high level development tool, MATLAB provides modeling and analysis of DSP algorithms. Through the use of Simulink and System Generator, these algorithms can be mapped into VHDL functions in CoSine’s UPL block.

Combining CoSine FPGA processing nodes with conventional DSP nodes is an effective overall solution to distributed multi-processor systems. While state machine processing is implemented in CoSine’s UPL block, the two internal CoSine embedded PowerPC’s can be tasked with hosting device drivers, performing message passing and handling interrupts. This further offloads conventional, power hungry DSP’s, freeing them for higher level analysis and intelligent, decision based processing.

Sensor Flow Diagram
Sensor Processing Data Flow


By offloading these computationally intensive functions from conventional DSP’s, overall system performance can be increased while reducing total board count, total power consumption and system cost.

Product Offerings
In addition to the ATCA form factor of the MM-333D development station, CoSine is being offered on Othello carriers for VXS VITA 41 and VITA 46. CoSine and Othello carriers are a perfect match that combined, provide one of the most powerful front end solutions available for next-generation signal processing equipment.

Last updated: Sep 12 2007, 10:39PM