MM-6463D - Six Channel 105 MSPS, 14-bit A/DC with dual RACE++

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Overview
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Datasheet

Standard Option	Six independent 14-bit 105MHz channels each with an optional Graychip DDC. Mechanism for common clock and software trigger/sync capable of coherently sampling multiple channels.
Variable Options	In addition to A/D conversion the MM-6463D can be configured for D/A conversion or as a digital receiver. Other A/D channel options include resolutions ranging from 8-bit to16-bits, up to eight total channels, and frequencies up to 2GHz.
RACE++ Ports	Two independent RACE++ ports on P2 connector in compliance with the RACE (Real time Asynchronous Compute Environment) ANSI/VITA 5.1-1999 standard.
PCI Memory Nodes	Two independent 64-bit/66MHz PCI memory nodes based on a proprietary ultra low latency core in compliance with the PCI-SIG® specification for the PCI 2.2 bus interface.
DMA Engines	Each memory node has a Mailbox DMA engine that supports linked-list (scatter/gather) chaining and generates a semaphore on the completion of a DMA transfer.
PCI Memory Arrays	Each PCI memory array can be configured with 512MB, 1GB, 2GB, or 4GB of SDRAM.
ECC	Each PCI memory node has an ECC engine that detects and corrects all single-bit errors, detects all double-bit errors, and some three and four bit errors within the same nibble.
PowerPC Processor	350MHz Motorola® 8245 PowerPC processor with MPC603e G2 superscalar core • L1 cache: 16K instruction cache, 16K data cache • I2O message interface • 256 byte nvSRAM • RS-232 Serial Port • Status Indicators and Controls • 128MB local SDRAM with ECC • Real-Time Clock • On-board Timers • Watchdog Timer and Alarms • COP & JTAG Test and Debug Interfaces
Processor Flash	32MB Flash
Protected Access	For security against inadvertent Flash programming or corruption, a hardware switch is provided to disable the Write Enable line to the Flash devices along with additional high security capabilities.
Gigabit Ethernet	On-board 10/100/1000 BaseT capable Ethernet Interface with integrated Gigabit Ethernet MAC and PHY layer functions supporting IEEE 802.3.
DMA Engines	The MM-6463D includes nine on-board DMA engines via the following devices: two for the A/D converters, two PCI memory nodes, two PCI-to-RACE++ bridges, PowerPC processor, Gigabit Ethernet Controller, and Universe II PCI-to-VME64 bridge.
Status Indicators and Controls	Six front panel LED’s indicate Ethernet and individual memory array status. Ethernet LED’s indicate link rate, two LED’s are software programmable, and one LED indicates processor BIST failure. A board reset signal is available and controlled by a push button switch.
Power Requirements	+5.0V Supply: 3.7A (Standby), 4.4A (Operate) +3.3V Supply: 6.3A (Standby), 10.5A (Operate)
Physical Dimensions	Height: 233.4 mm (9.2 in.) Depth: 160 mm (6.3 in.) Front Panel Height: 261.8 mm (10.3 in.) Width: 19.8 mm (0.8 in.) Maximum Component Height: 14.8 mm (0.58 in.) Weight: 22.5 ounces
Environmental Specifications	Operational Temperature: 0°C to +55°C, Ambient Storage Temperature: -40°C to +85°C
Vibration	Operating: 0.5 G, Non-operating: 1.0 G
Relative Humidity	0 – 95% Non-condensing
Altitude	0 – 10,0000 Feet
Airflow	200 LFM (Linear feet per minute) Minimum @ 55°C

Six 14-bit 105 MHz A/D channels
Dual RACE++ interfaces on P2
Capacity: 2GB, 4GB, 8GB
VME64 master/slave interface
On-board 350 MHz Motorola PowerPC processor with 128 MB local SDRAM
On-board Gigabit Ethernet
Up to 32MB Programmable Flash

The MM-6463D is a 6U VME board with six 14-bit 105MHz ADC channels and dual RACE++ on P2. Other features include a PowerPC processor, Gigabit Ethernet, VME64 master/slave interface and complete connectivity between all devices. Configurations are available with 2GB, 4GB, or 8GB of on-board SDRAM buffer memory.

The preconfigured module can act as a multi-channel A/D converter or Digital Receiver. Various versions of A/D conversion are supported, including utilization of optional Graychip DDC’s, customizable FPGA filtering, internal clock, and software trigger/sync capable of coherently sampling each channel.

By tightly coupling ADC’s or digital receivers to large amounts of memory, data can be effectively rate buffered before being transferred over the RACE++ switch fabric backplane. The dual RACE++ interfaces on P2 each operate at up to 267 MB/s, or concurrently at over 500 MB/s.

The PowerPC processor has 128MB of local SDRAM, up to 32MB of contiguous direct-mapped Flash, and a hardware Flash write-protect switch for high security environments. Other features include a DUART RS-232 serial port, programmable watchdog timer, Real-Time clock and RTC alarm, COP/JTAG, and front panel LED status indicators.

The PowerPC is utilized for hosting device drivers, setting up DMA transfers, scheduling tasks and message passing. The device drivers and well defined API’s are truly integrated into the VxWorks BSP, providing the flexibility and determinism expected from an embedded RTOS while balancing ease of use that results in a near plug and play solution.

A complete MC/OE API with “DX” like calls is provided for seamless interoperability in systems utilizing products from Mercury Computer Systems^®.

Reliability is ensured by extensive testing procedures. These include running diagnostics that stress multiple patterns and operations while cycling over various temperature ranges during burn-in.

Last updated: Oct 04 2007, 01:05AM

Six Channel 105 MSPS, 14-bit A/DC with dual RACE++

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Part Number	Description
MM-6463D/2G	Six Channel 105 MSPS, 14-bit A/DC with dual RACE++ with 2GB SDRAM (Two 1GB PCI memory nodes)
MM-6463D/4G	Six Channel 105 MSPS, 14-bit A/DC with dual RACE++ with 4GB SDRAM (Two 2GB PCI memory nodes)
MM-6463D/8G	Six Channel 105 MSPS, 14-bit A/DC with dual RACE++ with 8GB SDRAM (Two 4GB PCI memory nodes)

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MM-6463D Six Channel 105 MSPS, 14-bit A/DC with dual RACE++