Freescale's Power Architecture MPC8641D High-performance Dual or Single Core Processor

The MPC8641D is the latest generation e600 32-bit dual core processor from Freescale Semiconductor, Inc. The e600 has an on-board AltiVec^® 128-bit vector processor for efficient data movement and for math functions that rival a DSP.

L2 Cache
With a large backside L2 cache for each core, the e600 benefits from high bandwidth and low latency between the processor and the L2 cache. For applications that share data between cores, low latency data sharing features are also present.

DDR2 Memory Controllers
The device has dual 64-bit DDR2 memory controllers to match the bandwidth requirements of the two cores. The memory controllers can be assigned to each core for increased OS isolation, or can be shared between the cores. Accesses can be interleaved across both memory controllers, reducing the average latency to memory by increasing the number of open pages in a target memory region. Error correction codes implementing single error correction and double error detection can be optionally enabled to ensure that bit errors on the memory controller interface are corrected or at least reported to the cores. This is a requirement for any high-availability application.

PCI Express^® and Serial RapidIO^® Connectivity
There are two flexible high-performance I/O ports. Dual 8-lane PCI Express ports leverage PCI legacy with a high-performance serial point-to-point link that is commonly used to connect to a variety of other on-board high-performance devices. The 4-lane Serial RapidIO port, with its low software overhead, configuration simplicity, hardware error correction, and support for both memory mapped and packet-based transactions, is very well suited as a backplane interface.

Serial RapidIO is one of the embedded computing switched fabrics used for CPU-to-CPU communications. Using distributed switching of Serial RapidIO, system developers are able to have system topology freedom with four x4 links at 3.125 Gbps per 1x link without the need for a switch card.

Serial RapidIO used for CPU-to-CPU communications

PCI Express is frequently used in embedded computing as an I/O domain. Using a tree topology, one CPU controls a set of resources in the system which can be many levels deep and cascade through switches. Typically, PCI Express  x4/x8 links operate at 2.5 Gbps. A simple software model is provided in PCIe, so that users can get up and running quickly.

PCI Express used as an I/O domain

Ethernet Controller
There are four Ethernet controllers, supporting 10 Mbps, 100 Mbps, and 1000 Mbps. The Ethernet controllers have advanced capabilities for TCP and UPD checksum acceleration, QoS support, and packet header manipulation. Each Ethernet controller can be converted into a FIFO mode for high-efficiency ASIC connectivity.