Related Products:
AD3000 - 3 GSPS, 8-bit ADC XMC/PMC module with User Programmable Virtex-5 SX95T/LX110T FPGA
AD1500 - Dual Channel 1.5 GSPS, 8-bit ADC XMC/PMC module with User Programmable Virtex-5 SX95T/LX110T FPGA
M6000 - VXS I/O Controller with Dual PMC/XMC sites, Dual 4Gbit/s Fibre Channel, and User Programmable Virtex-4 FX60/100
VPF2 - PowerPC MPC8641D, Dual User Programmable Virtex-5 FPGA VXS Digital Signal Processor
FPE650 - Quad Xilinx Virtex-5 FPGA VPX Processor Board with Dual FMC Sites
HPE720 - 6U VPX Hybrid Processor Board with dual Xilinx Virtex-5 FPGAs and a MPC864xD
HPE640 - 6U VPX Hybrid Processing Engine with dual MPC8641D and dual Xilinx Virtex-5 FPGAs

FusionXF FPGA Development Kit, Software and HDL libraries for accessing FPGA functionality


  • Automatic discovery and configuration of FPGA resources
  • Extensive HDL libraries optimized for high performance FPGA processing and streaming data applications
  • Standard, easy to use, software API
  • Full source code provided for software, VHDL libraries and examples
  • Greatly reduces system design time
  • Allows designers to focus on key applications
  • Standardized across all VMETRO products for easy migration and upgrade path
  • Standardized tool chain with familiar, industry standard tools

When integrating FPGAs in embedded real-time DSP system designs, developers are faced with the challenges of developing and debugging their FPGA logic and software, moving data efficiently between CPU nodes and FPGA nodes, and integrating it all into their overall system design while staying on schedule and within budget. VMETRO’s FusionXF development kit addresses these challenges and provides system design engineers with powerful and optimized software and FPGA infrastructure to save them man years of implementation time.


FusionXF is a collection of software and associated HDL functions to aid customers in the development of their FPGA algorithms and logic for VMETRO’s customer-programmable FPGA products. It is targeted at reducing the design time and optimizing the performance of complex embedded real-time DSP systems comprised of multiple FPGA and PowerPC processors. It also supports the use of VMETRO FPGA-based products (e.g., an FPGA XMC module) on x86-based host platforms.

FusionXF provides all of the building blocks to build a fully functional FPGA design to which a customer can integrate their FPGA logic and algorithms. It contains software functionality to enable the control and utilization of FPGA resources from a PowerPC processor. And, it provides efficient data streaming between a processor and FPGAs, internally in an FPGA or between distributed FPGAs in a fabric. Figure 1 illustrates an example embedded real-time DSP system. The board on the left is a hybrid PowerPC and FPGA processing engine with two CPU nodes, two on-board FPGAs, and an XMC site that is populated with an FPGA XMC card. The board on the right is a quad-FPGA processing engine that is connected to the hybrid processor board via High-Speed Serial (HSS) links across the backplane. FusionXF has the software and HDL components to implement all of the data paths shown in Figure 1 as well the mechanisms to provide high-performance, low-latency, low-overhead data movement across the data paths.

FusionXF is comprised of an HDL Development Kit (HDK) that contains HDL functions and a Software Development Kit (SDK) that contains drivers, application software libraries, and utilities. Extensive documentation and illustrative HDL and software examples are included to aid developers. Figure 2 shows the software and corresponding HDL layers in FusionXF. The layered architecture of FusionXF makes it very easy to migrate applications from one hardware platform to another. Only the hardware specific Board Support IP (BSIP) and the Board Support Package (BSP) will change when changing hardware platforms. All other components are hardware independent.

Hardware
FusionXF is currently supported on all new VMETRO processing hosts and FPGA boards, including M6000, VPF2, HPE640, HPE720, FPE650 and AD1500/3000.

Last updated: Jul 18 2008, 03:45PM