MM-6171 2-4GB DDR2 SDRAM Buffer Memory XMC

The MM-6171 XMC is a Buffer Memory XMC with support for Serial RapidIO (sRIO) x4 or PCI Express (PCIe) x8. Equipped with 2-4GB of DDR2 SDRAM, the card provides high-speed buffering capabilities for DSP systems. The XMCs have a variety of uses, such as high-speed temporary storage, expanded system memory, interleaving, or for use with data aggregation and warehousing. The DDR2 SDRAM provides superior performance with low latency, while the bus interface with it’s full-featured DMA engine allows transactions to occur without host intervention.

Conforming to the VITA 42 mezzanine standard, the card interfaces to the host through the P15 connector. Four to eight high-speed serial links running at up to 3.125GHz provide a high-speed full duplex interface. Connecting these high-speed signals to the memory arrays is a Xilinx^® Virtex™-5 LX50T FPGA. The device is a memory controller, and is not designed to host User Programmable Logic (UPL) inside of it. Off of the LX50T are two independent memory arrays, each capable of interfacing to 1-2GB of DDR2 memory. Each array is 72-bits wide, with a 64-bit data path and ECC. Single bit errors are corrected and double-bit errors are detected through the memory controllers logic. The DDR2 arrays provide over 3GB/s of data bandwidth.

The MM-6171 also includes a fully verified bus interface and DMA engine. With sRIO, each link of the x4 bus interface runs at 3.125GHz. The sRIO DMA engine is a corner-turning, striding DMA engine, providing advanced functionality for DSP designs. For PCIe, each link of the x8 bus interface runs at 2.5GHz. The PCIe interface also comes with a full-featured DMA engine.

A device driver must be loaded for the card to function. VMETRO supports VxWorks 6.x and Linux 2.6.x for the MM-6171.